Arria V FPGA Family Overview

The 28-nm Arria^® V FPGA family balances cost and power with performance for mid-range applications, such as remote radio units, 10G/40G line cards, and in-studio mixers.

See the tables below for an overview of the Arria V FPGA and SoC FPGA family and package choices.

Arria V GX FPGA with 6.375-Gbps transceivers
Arria V GT FPGA with up to 10.3125-Gbps transceivers
Arria V SX SoC FPGA with ARM-based hard processor system (HPS) and 6.375-Gbps transceivers
Arria V ST SoC FPGA with ARM-based HPS and up to 10.3125-Gbps transceivers

Table 1. Arria V GX FPGA Family Overview (1)

Features	5AGXA1	5AGXA3	5AGXA5	5AGXA7	5AGXB1	5AGXB3	5AGXB5	5AGXB7
Equivalent logic elements (LEs)	75K	149K	190K	243K	300K	363K	420K	504K
Adaptive logic modules (ALMs)	28,302	56,100	71,698	91,680	113,208	136,880	158,491	190,240
M10K memory blocks	800	1,051	1,180	1,366	1,510	1,726	2,054	2,414
M10K memory (Kb)	8,000	10,510	11,800	13,660	15,100	17,260	20,540	24,140
Memory logic array blocks (MLABs) (Kb)	463	873	1,173	1,448	1,852	2,098	2,532	2,906
18x19 multipliers	480	792	1,200	1,600	1,840	2,090	2,184	2,312
Variable-precision digital signal processing (DSP) blocks	240	396	600	800	920	1,045	1,092	1,156
Maximum transceivers 6.375 Gbps	12	12	24	24	24	24	36	36
PCI Express^® (PCIe^®) hard intellectual property (IP) blocks	1	1	2	2	2	2	2	2
Maximum user I/O pins	416	416	544	544	704	704	704	704
Availability	Contact factory	Contact factory	Contact factory	Contact factory	Contact factory	Buy now	Contact factory	Contact factory

Table 2. Arria V GX FPGA Package Overview and User I/Os (I/Os, Transceivers) (2)

Device	5AGXA1	5AGXA3	5AGXA5	5AGXA7	5AGXB1	5AGXB3	5AGXB5	5AGXB7
F672 (27 mm)	336, 9	336, 9	336, 9	336, 9	-	-	-	-
F896 (31 mm)	416, 9	416, 9	384, 18	384, 18	384, 18	384, 18	-	-
F1152 (35 mm)	-	-	544, 24	544, 24	544, 24	544, 24	544, 24	544, 24
F1517 (40 mm)	-	-	-		704, 24	704, 24	704, 36	704, 36

Notes:

Arria V GX devices are offered in -3, -4, -5, and -6 speed grades.
Pin migration within each package.

Table 3. Arria V GT FPGA Family Overview (1)

Features	5AGTC3	5AGTC7	5AGTD3	5AGTD7
Equivalent LEs	149K	243K	363K	504K
ALMs	56,100	91,680	136,880	190,240
M10K memory blocks	1,051	1,366	1,726	2,414
M10K memory (Kb)	10,510	13,660	17,260	24,140
MLABs (Kb)	873	1,448	2,098	2,906
18x19 multipliers	792	1,600	2,090	2,312
Variable-precision DSP blocks	396	800	1,045	1,156
Maximum transceivers (6.375 Gbps / 10.3125 Gbps)	18 / 4	24 / 12	24 / 12	36 / 20
PCIehard IP blocks	1	2	2	2
Maximum user I/O pins	416	544	704	704

Notes:

10-Gbps transceivers are for chip-to-chip connections only.
Each set of three 6.375 Gbps transceivers can be configured as two 10-Gbps transceivers with the exception of one set in the F672 package and two sets in all other packages which have a maximum rate of 6.375 Gbps.

Table 4. Arria V GT FPGA Package Overview and User I/Os (I/Os, Maximum 6-Gbps Transceivers, Maximum 10-Gbps Transceivers) (2)

Device	5AGTC3	5AGTC7	5AGTD3	5AGTD7
F672 (27 mm)	336, 9, 4		-	-
F896 (31 mm)	416, 9, 4	384, 18, 8	384, 18, 8	-
F1152 (35 mm)	-	544, 24, 12	544, 24, 12	544, 24, 12
F1517 (40 mm)	-		704, 24, 12	704, 36, 20

Notes:

Arria V GT devices are offered in the -5 and -3 speed grades.
Pin migration within each package.
Each set of three 6.375-Gbps transceivers can be configured as two 10-Gbps transceivers with the exception of one set in the F672 package and two sets in all other packages which have a maximum rate of 6.375 Gbps.

Table 5. Industrial Temperature Support

Device	Package	Speed Grade
Arria V GT	F672, F896, F1152, F1517	I5, I3
Arria V GX	F672, F896, F1152, F1517	I5, I3

Table 6. Arria V SX SoC FPGA Family Overview

Features	5ASXB3	5ASXB5
Equivalent LEs	350,000	462,000
ALMs	132,075	174,340
M10K memory blocks	1,729	2,282
M10K memory (Kb)	17,288	22,820
MLABs (Kb)	2,014	2,658
18x19 multipliers	1,618	2,186
Variable-precision DSP blocks	809	1,068
Maximum transceivers 6.375 Gbps	30	30
PCIe hard IP blocks	2	2
Maximum FPGA user I/Os	528	528
Maximum HPS I/Os	216	216
FPGA hard memory controllers	3	3
HPS hard memory controllers	1	1
Processor cores (ARM^® Cortex^TM-A9)	Dual	Dual

Table 7. Arria V SX SoC FPGA Package Overview and User I/Os (FPGA IO, HPS I/Os, Transceivers)

Device/Package (mm x mm)	F896			F1152			F1517
	1.0 mm 31 x 31			1.0 mm 35 x 35			1.0 mm 40 x 40
	FPGA I/Os	HPS I/Os	Maximum Transceivers (6.375 Gbps)	FPGA I/Os	HPS I/Os	Maximum Tranceivers (6.375 Gbps)	FPGA I/Os	HPS I/Os	Maximum Transceivers (6.375 Gbps)
5ASXB3	170	216	12	350	216	18	528	216	30
5ASXB5	170	216	12	350	216	18	528	216	30

Table 8. Arria V ST SoC FPGA Family Overview

Features	5ASTD3	5ASTD5
Equivalent LEs	350,000	462,000
ALMs	132,075	174,340
M10K memory blocks	1,729	2,282
M10K memory (Kb)	17,288	22,820
MLABs (Kb)	2,014	2,658
18x19 multipliers	1,618	2,136
Variable-precision DSP blocks	809	1,068
Maximum transceivers (6.375 Gbps / 10.3125 Gbps)	30 / 16	30 / 16
PCIe hard IP blocks	2	2
Maximum FPGA user I/Os	528	528
Maximum HPS I/Os	216	216
FPGA hard memory controllers	1	1
HPS hard memory controllers	3	3
Processor cores (ARM Cortex-A9)	Dual	Dual

Notes:

10-Gbps transceivers are for chip-to-chip connections only.
Each set of three 6.375-Gbps transceivers can be configured as two 10-Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.375 Gbps.

Table 9. Arria V ST SoC FPGA Package Overview and User I/Os (I/Os, Transceivers)

Device/Package (mm x mm)	F896			F1152			F1517
	1.0 mm 31 x 31			1.0 mm 35 x 35			1.0 mm 40 x 40
	FPGA I/Os	HPS I/Os	Maximum Transceivers (6.375 Gbps / 10.3125 Gbps)	FPGA I/Os	HPS I/Os	Maximum Transceivers (6.375 Gbps / 10.3125 Gbps)	FPGA I/Os	HPS I/Os	Maximum Transceivers (6.375 Gbps / 10.3125 Gbps)
5ASTD3	170	216	12 / 4	350	216	18 / 8	528	216	30 / 16
5ASTD5	170	216	12 / 4	350	216	18 / 8	528	216	30 / 16

Notes:

Each set of three 6.375 Gbps transceivers can be configured as two 10-Gbps transceivers with the exception of the two sets nearest the PCIe hard IP which have a maximum rate of 6.375 Gbps.

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Arria V FPGA Family Overview

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