Transceivers Curriculum

A Transceivers/High-Speed I/O Protocol designer is a hardware engineer designing with multi-gigabit transceivers. This person could also be designing the PCB for the FPGA and needs to solve signal integrity issues.

Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.

Online Training
Read Me First! (ORMF1000)  (0.5 hours) 简体中文 (OCRMF1000) (0.5 hours) 日本語 (OJRMF1000) (0.5 hours)
Setting up Floating Licenses (ODSW1040)  (0.5 hours)
Basics of Programmable Logic (ODSW1005)  (1.5 hours) 简体中文 (OCDSW1005) (1 hour) 日本語 (OJDSW1005) (1 hour)
How to Begin a Simple FPGA Design (ODSW1010)  (1 hour) 简体中文 (OCDSW1010) (1 hour) 日本語 (OJDSW1010) (1 hour)
VHDL Basics (OHDL1110) (1.5 hours) 简体中文 (OCHDL1110) (1 hour)		Verilog HDL Basics (OHDL1120) (1 hour) 简体中文 (OCHDL1120) (0.5 hours)
	or	or
		SystemVerilog with the Quartus II Software (OHDL1125) (1 hour) 简体中文 (OCHDL1125) (1 hour) 日本語 (OJHDL1125) (0.5 hours)
Synplify Pro Tips and Tricks (OSYN1100) (1 hour)
The Quartus II Software Interactive Tutorial (ODSW1050) (4 hours)
Using the Quartus II Software: An Introduction (ODSW1100) (1.5 hours) 简体中文 (OCDSW1100) (1.5 hours) 日本語 (OJDSW1100) (2 hours) or The Quartus II Software Design Series: Foundation (ODSW1110) (8 hours) 简体中文 (OCDSW1110) Quartus II V9.0 基礎編-1 Settings と Assignments (OJDSW1111) (1 hour) I/O System Design (ODSW1107)  (2 hours) 日本語 (OJDSW1112) (0.5 hours) 简体中文 (OCDSW1107) (2 hours) Advanced I/O System Design (ODSW1108)  (1.5 hours) 简体中文 (OCDSW1108)  (1.5 hours) TimeQuest Timing Analyzer (ODSW1115) (2 hours) 简体中文 (OCDSW1115)  (2 hours) 日本語 (OJDSW1115) (OJFDSW1115) (0.5 hours) (2 hours) Timing Closure Using TimeQuest Custom Reporting (OTIM1100) (0.5 hours)
What's New in the Quartus II Software Version 11.0 (ODSW1103) (0.5 hours)
Overview of Mentor Graphic's ModelSim Software (ODSW1120) (1 hour) 日本語 (OJDSW1120) (1 hour)	and/ or	Simulating Designs with 3rd Party EDA Simulators (ODSW1122) (1 hour)
Transceiver Basics (OSIIGX1115) (0.5 hours) 简体中文 (OCEMB1115)  (0.5 hours) 日本語 (OJSIIGX1115)  (1 hour)
Stratix V Transceiver Architecture: PMA and PCS Features & Protocol Support (OSV1100) (1 hour)
External Memory Solutions Overview (OMEM1109) (0.5 hours)
Using High Performance Memory Interfaces in Altera FPGAs (OMEM1110) (2 hours)
Protocol-Specific Training  (please see table below for more details)
Stratix V Transceiver Design Flow and Dynamic Reconfiguration (OSV1103)  (1 hour)
Dynamic Reconfiguration in Altera Transceiver Devices (OSIV1110)  (1.5 hours) 简体中文 (OCSIV1110) (1.5 hours)	or	Transceiver Reconfiguration in Altera 28-nm Devices (OXRE1010)  (1.5 hours)
Advanced Signal Conditioning for Stratix IV and Stratix V Receivers (OSV1105)  (0.5 hours)
Decision Feedback Equalization and Adaptive Equalization in Stratix IV GX/GT Devices (OSIV1100)  (0.5 hours)
Transceiver Toolkit (OTCVR1100)  (0.5 hours)
Power Distribution Network Design for Stratix III and Stratix IV (ODPN1100) (0.5 hours) 简体中文 (OCPDN1100) (0.5 hours)
Power Distribution Network Design Using Altera PDN Design Tools (OPDN1105) (0.5 hours)

Protocol-Specific Training

Custom Protocol Design in Altera 28-nm Devices (O28CP1110) (2 hours)	Getting Started with PCI Express Designs in Altera Transceiver Devices (OPCI1101) (2 hours)	Introduction to Altera's 10/100/1000 Mb Ethernet Solutions (OTSE1116) (1.5 hours) 简体中文 (OCTSE1115) (1.5 hours)
Serial RapidIO Design with Altera 40nm Devices (ORIO1115) (2 hours) 简体中文 (OCRIO1115) (1.5 hours)	Triple-rate SDI (OSDI1110)  (0.5 hours)	Introduction to Altera's 10Gb Ethernet Solutions (OETH1118)  (1.5 hours)
Getting Started with Altera’s 28-nm PCI Express Solutions (OPCI1102)  (1 hour)	High-Speed Serial Protocol Design with Altera Transceiver Devices (O40NM1110) (2.5 hours) 简体中文 (OC40NM1110) (2.5 hours)

Instructor-led / Virtual Classroom Training
Best Practices for Maximizing FPGA Design Productivity (IPRO200) (16 hours)
Introduction to VHDL (IHDL110) (8 hours)	or	Introduction to Verilog HDL (IHDL120) (8 hours)
The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours)
The Quartus II Software Design Series: Timing Analysis (IDSW120) (8 hours)
Advanced Timing Analysis with TimeQuest (IDSW125) (8 hours)
The Quartus II Software Debug and Analysis Tools (IDSW135) (8 hours)
Building Gigabit Interfaces in Altera Transceiver Devices (ITRNSCVR) (8 hours)
Implementing, Simulating, and Debugging External Memory Interfaces (IMEM210) (8 hours)
Timing Closure with the Quartus II Software (IDSW145)  (8 hours)	and/ or	Design Optimization Using Quartus II Incremental Compilation (IDSW142) (8 hours)
Advanced VHDL Design Techniques (IHDL240)  (8 hours)	or	Advanced Verilog HDL Design Techniques (IHDL230)  8 hours)