Documentation: Stratix IV Devices

BSDL Files

Stratix IV Device Handbook (31 MB)

Stratix IV Device Handbook Volume 1: Device Interfaces and Integration (ver 4.5, Dec 2011)

Section I. Device Core

Chapter 1. Overview for the Stratix IV Device Family HTML | PDF (ver 3.3, June 2011)
Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices HTML | PDF (ver 3.1, Feb 2011)
Chapter 3. TriMatrix Embedded Memory Blocks in Stratix IV Devices HTML | PDF (ver 3.3, Dec 2011)
Chapter 4. DSP Blocks in Stratix IV Devices HTML | PDF (ver 3.1, Feb 2011)
Chapter 5. Clock Networks and PLLs in Stratix IV Devices HTML | PDF (ver 3.3, Dec 2011)

Section II. I/O Interfaces

Chapter 6. I/O Features in Stratix IV Devices HTML | PDF (ver 3.3, Dec 2011)
Chapter 7. External Memory Interfaces in Stratix IV Devices HTML | PDF (ver 3.2, Feb 2011)
Chapter 8. High Speed Differential I/O Interfaces with DPA in Stratix IV Devices HTML | PDF (ver 3.3, Dec 2011)

Section III. System Integration

Chapter 9. Hot Socketing and Power-On Reset in Stratix IV Devices HTML | PDF (ver 3.2, Feb 2011)
Chapter 10. Configuration, Design Security, Remote System Upgrades with Stratix IV Devices HTML | PDF (ver 3.4, Dec 2011)
Chapter 11. SEU Mitigation in Stratix IV Devices HTML | PDF (ver 3.2, Feb 2011)
Chapter 12. JTAG Boundary Scan Testing in Stratix IV Devices HTML | PDF (ver 3.2, Feb 2011)
Chapter 13. Power Management in Stratix IV Devices HTML | PDF (ver 3.2, Feb 2011, )

Stratix IV Device Handbook Volume 2: Transceivers (ver 4.3, Dec 2011)

Section I. Transceiver Architecture

Chapter 1. Transceiver Architecture in Stratix IV Devices HTML | PDF (ver 4.4, Dec 2011)
Chapter 2. Transceiver Clocking in Stratix IV Devices HTML | PDF (ver 3.3, Dec 2011)
Chapter 3. Configuring Multiple Protocols and Data Rates in Stratix IV Devices HTML | PDF (ver 4.1, Feb 2011)
Chapter 4. Reset Control and Power Down in Stratix IV Devices HTML | PDF (ver 4.2, Dec 2011)
Chapter 5. Dynamic Reconfiguration in Stratix IV Devices HTML | PDF (ver 3.3, Dec 2011)

Stratix IV Device Handbook Volume 3: Transceiver Configuration Guide (ver 4.2, Dec 2011)

Section I. Transceiver Configuration Guide

Chapter 1. ALTGX Transceiver Setup Guide for Stratix IV Devices HTML | PDF (ver 4.2, Dec 2011)
Chapter 2. Transceiver Design Flow Guide for Stratix IV Devices HTML | PDF (ver 4.1, Feb 2011)
Chapter 3. ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices HTML | PDF (ver 3.1, Feb 2011)

Statix IV Device Handbook Volume 4: Device Datasheet and Addendum (ver 5.2, Dec 2011)

Section I. Device Datasheet and Addendum for Stratix IV Devices

Chapter 1. DC and Switching Characteristics for Stratix IV Devices HTML | PDF (ver 5.2, Dec 2011)

Stratix IV I/O Timing Spreadsheet (xls)

Chapter 2. Addendum to the Stratix IV Device Handbook HTML | PDF (ver 1.5, Feb 2011)

Related Documentation

External Memory Interfaces

AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices (ver 1.2, Feb 2010, 986 KB)
Design Example for AN 461 (3 MB)
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)

Power and Thermal Management

Stratix III, Stratix IV, Stratix V, HardCopy III and HardCopy IV PowerPlay Early Power Estimator (ver 11.1 SP2, Jan 2012, 7 KB)
PowerPlay Early Power Estimator User Guide (1 MB)
40-nm FPGA Power Management and Advantages (ver 1.2, Dec 2008, 2 MB)
Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
AN 514: Power Optimization in Stratix IV FPGAs (ver 1.0, May 2008, 221 KB)
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology (ver 1.0, May 2009, 899 KB)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (ver 1.0, Jul 2009, 878 KB)
AN 583: VCC to VCCDPLL Spice Examples (159 KB)
Device-Specific Power Delivery Network (PDN) Tool User Guide (ver 1.0, Nov 2009, 880 KB)
     Power Delivery Network (PDN) Tool Version 11.1 for Cyclone V, Arria V, Stratix V, Cyclone IV, and Arria II GZ Devices (3 MB)
     Power Delivery Network (PDN) Tool for Arria II GX Devices (2 MB)
     Power Deliver Network (PDN) Tool for Stratix IV Devices (2 MB)
     Power Delivery Network (PDN) Tool for Stratix III Devices (2 MB)
Power Delivery Network (PDN) Tool User Guide (ver 2.0, Apr 2009, 763 KB)
Power Delivery Network (PDN) Tool (2 MB)
PowerPlay Early Power Estimator User Guide (ver 6.0, Jan 2012, 2 MB)
Voltage Regulator Selection for FPGAs (ver 1.0, Nov 2008, 306 KB)

I/O Interfaces, Protocols and Signal Integrity

AN 456: PCI Express High Performance Reference Design (ver 1.3, Sep 2010, 535 KB)
AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (ver 1.1, Jan 2011, 1 MB)
AN 529: Via Optimization Techniques for High-Speed Channel Designs (ver 1.0, May 2008, 690 KB)
AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs (ver 1.0, May 2008, 208 KB)
IP Compiler for PCI Express User Guide (ver 11.0, May 2011, 7 MB)
Transceiver Poster (ver 1.0, Feb 2009, 191 KB)
Triple Speed Ethernet MegaCore Function User Guide (ver 2.2, Nov 2011, 2 MB)
Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
AN 454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices (ver 3.0, Sep 2011, 1 MB)
Design Examples 1 (412 KB)
Design Examples 2 (236 KB)
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs (ver 2.0, Jan 2011, 821 KB)
AN 553: Debugging Transceivers (ver 1.1, Dec 2009, 1 MB)
AN 553: Design Files (874 KB)
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices (ver 1.1, Sep 2011, 1 MB)
(Not applicable when designing with Stratix IV GT engineering sample devices)
AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices (ver 1.1, Mar 2012, 638 KB)
AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices (ver 2.0, Jan 2010, 284 KB)
(Not applicable when designing with Stratix IV GT engineering sample devices)
AN 573: Implementing the Interlaken Protocol in Stratix IV Transceivers (ver 1.1, Dec 2009, 768 KB)
(Not applicable when designing with Stratix IV GX and Stratix IV GT engineering sample devices)
AN 577: Recommended Protocol Configurations for Stratix IV GX FPGAs (ver 3.0, Mar 2011, 869 KB)
AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT Devices (ver 1.0, May 2009, 1 MB)
AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode (ver 3.0, Jan 2011, 709 KB)
AN580_scripts.zip (17 KB)
AN 602: Understanding the Pre-Emphasis and Linear Equalization Features in Stratix IV GX Devices (ver 1.0, Nov 2010, 2 MB)
AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices (ver 1.0, Jul 2010, 2 MB)
AN 635: Implementing SATA and SAS Protocols in Altera Devices (ver 1.0, Jun 2011, 584 KB)
Early SSN Estimator User Guide for Altera Programmable Devices (ver 1.0, Nov 2009, 788 KB)
Stratix IV Early SSN Estimator (615 KB)
HST Jitter and BER Estimator Tool User Guide for Stratix IV GX and GT Devices (ver 1.0, Jul 2010, 1 MB)
PCI Express hard intellectual property solutions from Altera (ver 2.0, Jul 2009, 165 KB)
Understanding 40-nm FPGA Solutions for SATA/SAS (ver 2.0, Jul 2010, 404 KB)

DSP

40-nm Stratix IV FPGAs and HardCopy IV ASICs (ver 1.1, Sep 2008, 372 KB)
Altera Product Catalog (ver 11.1, Feb 2012, 6 MB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Versatile Digital QAM Modulator (ver 2.0, Dec 2010, 553 KB)

Device Configuration and Remote System Upgrades

AN 603: Active Serial Remote System Upgrade Reference Design (ver 1.0, Apr 2010, 894 KB)
AN603 Design Files (1 MB)

Design Guidelines

AN 519: Stratix IV Design Guidelines (ver 1.1, May 2009, 493 KB)
AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III and Stratix IV Devices (ver 1.2, Feb 2010, 986 KB)
Design Example for AN 461 (3 MB)
AN 553: Debugging Transceivers (ver 1.1, Dec 2009, 1 MB)
AN 553: Design Files (874 KB)
AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology (ver 1.0, May 2009, 899 KB)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (ver 1.0, Jul 2009, 878 KB)
AN 583: VCC to VCCDPLL Spice Examples (159 KB)
AN 603: Active Serial Remote System Upgrade Reference Design (ver 1.0, Apr 2010, 894 KB)
AN603 Design Files (1 MB)
AN 611: Mapping 3G-SDI Level B and Dual Link HD-SDI (SMPTE372) Reference Design (ver 1.0, Dec 2010, 987 KB)
Design Files for AN611 (839 KB)
AN 658: Best Design Practices for HardCopy Devices (ver 1.0, Apr 2012, 768 KB)
Avoiding PCB Design Mistakes in FPGA-Based Systems (ver 1.0, Mar 2009, 935 KB)
(Taray Inc.)
Stratix IV GX and Stratix IV E Device Family Pin Connection Guidelines (ver 1.6, Jun 2011, 339 KB)

PCB Layout and Packaging

AN 553: Debugging Transceivers (ver 1.1, Dec 2009, 1 MB)
AN 553: Design Files (874 KB)

Development Kits

100G Development Kit, Stratix IV GT Edition Reference Manual (ver 1.0, Sep 2010, 2 MB)
Altera Product Catalog (ver 11.1, Feb 2012, 6 MB)
SDI HSMC Reference Manual (ver 1.0, Jul 2009, 1 MB)
Stratix IV E FPGA Development Board Reference Manual (ver 1.2, Jun 2011, 1 MB)
Stratix IV GX FPGA Development Board Reference Manual (ver 2.2, Aug 2010, 2 MB)
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual (ver 1.0, Nov 2010, 2 MB)
Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Reference Manual (ver 1.1, Oct 2011, 1 MB)
Audio Video Development Kit, Stratix IV GX Edition User Guide (ver 2.0, Nov 2009, 1 MB)
Stratix IV E FPGA Development Kit User Guide (ver 2.1, Aug 2011, 3 MB)
Stratix IV GT 100G Development Kit User Guide (ver 1.1, Oct 2010, 4 MB)
Stratix IV GX FPGA Development Kit User Guide (ver 2.1, Aug 2010, 3 MB)
Stratix IV GX FPGA Development Kit, 530 Edition User Guide (ver 1.0, Nov 2010, 3 MB)
Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Guide (ver 1.1, Feb 2012, 972 KB)
Transceiver Signal Integrity Development Kit, Stratix IV GX Edition Reference Manual (ver 2.1, Oct 2011, 1 MB)
Transceiver Signal Integrity Development Kit, Stratix IV GX Edition User Guide (ver 2.1, Jan 2012, 1,014 KB)

End Applications

40-nm FPGAs and the Defense Electronic Design Organization (ver 1.0, Jul 2008, 313 KB)
Anti-Tamper Capabilities in FPGA Designs (ver 1.0, Jul 2008, 310 KB)
Assessing FPGA DSP Benchmarks at 40 nm (ver 1.0, Mar 2009, 463 KB)
Designing Basestation Channel Cards with FPGAs (ver 4.1, Mar 2012, 131 KB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Designing Remote Radio Head Applications with FPGAs (ver 3.0, Feb 2012, 381 KB)
DO-254 Support for FPGA Design Flows (ver 1.0, Jul 2008, 91 KB)
DO-254-certifiable IP cores (ver 2.0, Nov 2008, 119 KB)
FPGA companion chip solutions from Altera (ver 2.0, Nov 2010, 674 KB)
FPGA Coprocessing Evolution: Sustained Performance Approaches Peak Performance (ver 1.1, Jun 2009, 303 KB)
Military Benefits of the Managed Risk Process at 40 nm (ver 1.0, Jul 2008, 993 KB)
Military Productivity Factors in Large FPGA Designs (ver 1.0, Jul 2008, 443 KB)
Optical Transport Networks for 100G Implementation in FPGAs (ver 1.1, Jul 2010, 689 KB)
Power-Optimized Solutions for Telecom Applications (ver 1.0, Jan 2009, 594 KB)
Remote Radio Heads and the Evolution Towards 4G Networks (ver 1.1, Feb 2009, 718 KB)
(Radiocomp)
Versatile Digital QAM Modulator (ver 2.0, Dec 2010, 553 KB)
Wireless End Market Solutions (ver 4.1, Jul 2010, 144 KB)

General Device Documentation

40-nm Stratix IV FPGAs and HardCopy IV ASICs (ver 1.1, Sep 2008, 372 KB)
40-nm FPGAs: Architecture and Performance Comparison (ver 1.0, Dec 2008, 2 MB)
Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB)
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming (ver 5.0, Dec 2010, 1,004 KB)
FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, Apr 2009, 3 MB)
Innovating With a Full Spectrum of 40-nm FPGAs and ASICs With Transceivers (ver 1.4, Jul 2010, 663 KB)
Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.1, Feb 2009, 377 KB)
Using 10-Gbps Transceivers in 40G/100G Applications (ver 1.4, Sep 2011, 603 KB)

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