IP Support for Arria V and Cyclone V FPGA Families
- Please see the Intellectual Property (IP) page for the complete list of supported IP cores
PCI Express Updates
The following updates are available in Quartus® II software v11.1:
- PCI Express® Gen3 compilation support
- Stratix® V Hard IP for PCI Express
- 256-bit Avalon® Streaming (Avalon-ST) interface
- 128-bit Avalon-ST interface
- Avalon-MM Stratix V Hard IP for PCI Express
- 128-bit Avalon Memory-Mapped (Avalon-MM) interface
- Arria® V Hard IP for PCI Express
- 128-bit Avalon-ST interface
- Cyclone® V Hard IP for PCI Express
- 128-bit Avalon-ST interface
The latest device family support are available on this page.
Table 1. Altera IP Core Device Support Levels
| FPGA Device Families | HardCopy ASIC Device Family |
|---|---|
Preliminary support |
HardCopy Companion The IP core is verified with preliminary timing models for the HardCopy® ASIC companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy ASIC device family. It can be used in production designs with caution. |
Final support |
HardCopy Compilation The IP core is verified with final timing models for the HardCopy ASIC device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. |
Table 2. Updated IP Core Device Support Levels
| IP Core | Device Family | Support |
|---|---|---|
| 10-Gbps Ethernet MAC MegaCore® function | HardCopy IV |
HardCopy Companion |
| 10GBASE-R PHY IP core | Stratix V |
Preliminary |
| Arria V Hard IP for PCI Express | Arria V |
Preliminary |
| Avalon-MM Stratix V Hard IP for PCI Express | Stratix V |
Preliminary |
| CIC MegaCore function |
Cyclone V |
Preliminary |
Arria V |
Preliminary |
|
Stratix V |
Preliminary |
|
| CPRI MegaCore function |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| Custom PHY IP core |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| Cyclone V Hard IP for PCI Express | Cyclone V | Preliminary |
| DDR SDRAM Controller with ALTMEMPHY IP | HardCopy II | HardCopy Compilation |
| DDR2 SDRAM Controller with ALTMEMPHY IP | HardCopy II | HardCopy Compilation |
| DDR2/3 SDRAM Controllers with UniPHY |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| HardCopy III | HardCopy Compilation | |
| HardCopy IV | HardCopy Compilation | |
Deterministic Latency PHY IP core |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| FIR Compiler |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| FIR Compiler II MegaCore function |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| FFT MegaCore function |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| Interlaken PHY IP core | Stratix V | Preliminary |
| Low Latency PHY IP core | Stratix V | Preliminary |
| NCO MegaCore function |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| PCI Compiler |
Cyclone III LS | Final |
| Cyclone IV GX | Final | |
| HardCopy III | HardCopy Companion | |
| HardCopy IV | HardCopy Companion | |
| PHY IP Core for PCI Express | Stratix V | Preliminary |
| QDR II and QDR II+ SRAM Controllers with UniPHY |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| HardCopy III | HardCopy Compilation | |
| HardCopy IV | HardCopy Compilation | |
| RapidIO® MegaCore function |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| Reed-Solomon Compiler |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| Reed-Solomon II MegaCore function |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| RLDRAM II Controller with UniPHY |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| HardCopy III | HardCopy Compilation | |
| HardCopy IV | HardCopy Compilation | |
| Serial Digital Interface (SDI) MegaCore function |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| Stratix V Hard IP for PCI Express | Stratix V | Preliminary |
| Triple-Speed Ethernet MegaCore function |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| Video and Image Processing Suite |
Arria V | Preliminary |
| Stratix V | Preliminary | |
| Viterbi Compiler |
Cyclone V | Preliminary |
| Arria V | Preliminary | |
| Stratix V | Preliminary | |
| XAUI PHY IP core | Stratix V | Preliminary |
