Interlaken is a scalable, chip-to-chip interconnect protocol designed to enable transmission speeds from 10 to 100 Gbps and beyond. Using the latest transceiver technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnects and provides a scalable solution that can be used throughout an entire system. The scalability comes from Interlaken's ability to run over a variable number of lanes with no inherent limit on the data rate per lane.
Addressing the shortcomings of existing chip-to-chip protocols, Interlaken combines the channelization and flow control attributes of SPI 4.2 with the long reach and low pin count requirements of XAUI. Bundles of serial links create logical chip-to-chip connections with multiple channels, backpressure capability, cyclic redundancy check (CRC)-based data integrity checking, and flexible lane configuration.
Altera's high-speed devices (see Table 1), used in conjunction with an Altera® Interlaken intellectual property (IP) core optimized for FPGAs, provide an ideal platform on which to implement one or more Interlaken interfaces.
| Table 1. Device Support for Interlaken | |
| Device | Channels/Data Rate (Gbps) |
|---|---|
| Stratix® V GT FPGAs | Up to 4 channels at rates up to 28 Gbps and 32 channels at rates up to 12.5 Gbps |
| Stratix V GX | Up to 66 channels at rates 14.1 Gbps |
| Stratix V GS | Up to 48 channels at rates 14.1 Gbps |
| Stratix IV GT FPGAs | Up to 32 channels at rates up to 11.3 Gbps, or up to 40 channels at rates up to 6.375 Gbps |
| Stratix IV GX FPGAs | Up to 40 channels at rates up to 6.375 Gbps |
| Stratix II GX FPGAs | Up to 20 channels at rates up to 6.375 Gbps |
| Arria II GZ FPGAs | Up to 24 channels at rates up to 6.375 Gbps |
| HardCopy® V ASICs | Up to 48 channels at rates up to 6.375 Gbps |
| HardCopy IV GX ASICs | Up to 16 channels at rates up to 6.5+ Gbps, and up to 8 additional channels at rates up to 3.2 Gbps |
The Stratix V series FPGA implementation is specifically optimized to take advantage of the hardened 64/67 encoder-decoder blocks, CRC , scrambler, gearbox, as well as advanced structures available today in FPGAs. Altera's Interlaken core supports 10, 40, and 100 Gbps, with any number of transceiver lanes. Each core is fully compliant to the Interlaken revision 1.2 specifications, and provides a cost-effective, risk-free, and quick time-to-market solution.
Figure 1. Interlaken IP on Stratix V FPGA
Related Links
Devices
- Stratix V FPGAs
- Stratix IV FPGAs
- Arria II FPGAs
- HardCopy V ASICs
- HardCopy IV ASICs
- Stratix II GX FPGAs
