RLDRAM is a low-latency DRAM with SRAM-like random access. RLDRAM outperforms DDR3 in sustaining high bandwidth and is utilized for high-end networking applications that require back-to-back read and write operations. Altera's Stratix® V FPGA supports RLDRAM III with a speed up to 1,600 Mbps.
Table 1 lists the features of RLDRAM II and RLDRAM III.
| Table 1. RLDRAM II and RLDRAM III Features | |||
| Feature | RLDRAM II | RLDRAM III | |
|---|---|---|---|
| Voltage (core; I/Os) | 1.8; 1.5 / 1.8 |
1.35; 1.2 |
|
| Clock | 533 MHz |
1,067 MHz |
|
| Data rate | 1,067 Mbps |
2,133 Mbps |
|
| Row cycle time (tRC) | 15 ns |
Less than 10 ns |
|
| Density | 576 Mb |
576 Mb (stackable to 1 Gb) |
|
| Multibank write | N/A |
2 to 4 banks |
|
| Banks | 8 |
16 |
|
| Termination (ODT to VDDQ/2) | 150 ohm |
40, 60, 120 ohm |
|
| Output drive | 25 to 60 ohm |
40, 60 ohm |
|
| Burst length | 2, 4, 8 |
2, 4, 8 |
|
| Training | N/A |
Read training |
|
| Data read strobe | Per word |
Per byte |
|
| Data masking | 1 mask bit/36DQs |
2 mask bits/36DQs |
|
| Refresh | Bank dependent |
Bank dependent (multibank capable) |
|
| Reset pin | N/A |
Included |
|
