Arria GX FPGA Signal Integrity Center

Arria^® GX FPGAs deliver solid signal integrity by providing transceivers with excellent jitter characteristics on a flip-chip package.

Arria GX transceiver features

The protocol-specific transceivers are tuned to meet and exceed standards compliancy with the following features:

• Serial transceiver channels with clock/data recovery support operating speeds up to 3.125 Gbps
• Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels
• Support for CDR-based bus standards such as PCI Express, Gigabit Ethernet, and Serial RapidIO^® 
• 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
• Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
• 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers
• Refer to the transceiver block characteristics in the Arria GX device data sheet (PDF) for DC and switching specifications

Figure 1. Arria GX Transceiver at 2.5 Gbps

Arria GX signal integrity features

Table 1 provides a list of the signal integrity features in Arria GX devices to support the FPGA architecture and to simplify PCB design.

Documentation

• Arria GX Device Handbook
  • Arria GX Transceiver Architecture Overview (PDF)
  • Selectable I/O Standards in Arria GX Devices (PDF)
  • High-Speed Source-Synchronous Differential I/O Interfaces in Arria GX Devices (PDF) 
  • Package Information for Arria GX Devices (PDF)
• Application notes
  • Guidelines for Designing High-Speed FPGA PCBs (PDF) 
• White papers
  • Basic Principles of Signal Integrity (PDF)